Method, system, and program for an adaptor to read and write to system memory

ABSTRACT

Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method, system, and program for anadaptor to read and write to system memory.

2. Description of the Related Art

In certain computing environments, multiple host systems may communicatewith one or more control units, such as an IBM Enterprise Storage Server(ESS)®, for data in a storage device managed by the ESS receiving therequest. The control unit manages access to storage devices, such asinterconnected hard disk drives through one or more logical paths. (IBMand ESS are registered trademarks of IBM). The interconnected drives maybe configured as a Direct Access Storage Device (DASD), Redundant Arrayof Independent Disks (RAID), Just a Bunch of Disks (JBOD), etc. Thecontrol unit includes a host adaptor to receive I/O requests from thehost. In certain systems, the host may read and write blocks of datahaving a certain format, such as 512 byte blocks and the control unitmay store data in a different format by adding metadata to the blocksfrom the host, resulting in 524 bytes per block.

In one system, the host adaptor may transfer blocks to write to logicalblock addresses to a memory controller for a cache. The memorycontroller may then handle the virtual address mapping of the logicalblocks to write to the physical pages in the cache. When requestingdata, the host adaptor may provide the memory controller the logicalblocks to read and the memory controller may translate the requestedlogical blocks to physical pages in the cache. The memory controllerthen fetches the data from the determined physical pages to return tothe host adaptor to, in turn, return to the host.

SUMMARY

Provided are a method, system, and program for an adaptor to read andwrite to system memory. A plurality of blocks of data to write tostorage are received at an adaptor. The blocks of data are added to abuffer in the adaptor. A determination is made of pages in a memorydevice and I/O requests are generated to write the blocks in the bufferto the determined pages, wherein two I/O requests are generated to writeto one block split between two pages in the memory device. The adaptorexecutes the generated I/O requests to write the blocks in the buffer tothe determined pages in the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a computing environment.

FIG. 2 illustrates an embodiment of a page mapping.

FIG. 3 illustrates information in an I/O request.

FIGS. 4 and 5 illustrate an embodiment of operations to write data.

FIG. 6 illustrates an embodiment of operations to read data.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a computing environment. One or morehosts 2 communicate Input/Output (I/O) requests directed to one or morestorage systems 4 (only one is shown) to a control unit 6, where thecontrol unit 6 manages access to the storage system 4. The control unit6 includes a host adaptor 8 to enable network communication with thehosts 2 and a device adaptor 10 enabling communication with one or morestorage systems 4. The control unit 6 further includes a processor 12that executes I/O code 14 to manage I/O requests and a cache 16 to storeupdates to data in the storage system 4 or data requested by the hosts2. A non-volatile storage system (NVS) 18 is used to provide anadditional non-volatile backup of updates to data in the storage system4, such as a battery backed-up memory device. Bus 19 enablescommunication between the different control unit 6 components and maycomprise one or more bus interfaces. The control unit 6 may include adual processor system, with an additional processor, cache and NVS.

The host adaptor 8 includes a sequence buffer 20 to store blocks of datain the storage system 4 to return to the host 2 or to update in thestorage system 4. A split buffer 21 within the sequence buffer is usedto buffer split blocks as described below. The host adaptor 8 furtherincludes an adaptor controller 22 that includes firmware or code toperform the host adaptor operations 8 and a Direct Memory Access (DMA)engine 24 that enables the host adaptor 8 to read or write directly tothe cache 16 and NVS 18 without going through the processor 12. Theadaptor controller 22 builds a page mapping 26 that provides a mappingof logical blocks, such as Logical Block Addresses (LBAs) in one or morelogical tracks, to physical pages in the cache 16. The adaptorcontroller 22 uses the page mapping 26 to generate DMA I/O requests tocause the DMA engine 24 to read or write logical blocks at thecorresponding pages identified in the page mapping 26.

The hosts 2, storage system 4, and control unit 6 may communicate over anetwork (not shown), which may comprise a local area network (LAN),storage area network (SAN), bus interface, serial interface, etc. Thecontrol unit 6 may comprise any type of server, such as an enterprisestorage server, storage controller, etc., or other device used to manageI/O requests to attached storage system 4. The storage system 4 mayinclude storage devices known in the art, such as interconnected harddisk drives (e.g., configured as a DASD, RAID, JBOD, etc.), magnetictape, electronic memory, etc.

FIG. 2 illustrates an example of an embodiment of the page mapping 26 asshowing how each logical block subject to an I/O request maps tophysical pages in the cache 16. The control unit 6 may maintain multiplepage mappings 26 if the control unit 6 writes logical blocks to bothcache 16 and NVS 28, where one page mapping would provide thecorrespondence of logical blocks to pages in the cache 16 and anotherpage mapping would provide the correspondence of logical blocks to pagesin the NVS 18. The page mapping 26 may include a page index of the pageincluding the corresponding logical block. In one implementation, thestart location of the page in the memory (cache 16 or NVS 18)corresponding to the page ID can be determined by multiplying the pagesize, e.g., 4 kilobytes (KB), times the index number. Consecutivelogical blocks may map to discontiguous pages in the cache 16 and NVS28.

FIG. 3 illustrates an embodiment of information in the DMA I/O request50 the adaptor controller 22 generates to cause the DMA engine 24 toread or write data directly at the cache 16 or NVS 18. The DMA request50 includes an I/O type 52 indicating whether the request is to read orwrite; a source address 54 indicating the location in the sequencebuffer 20 from which updated data is written; a destination address 56indicating the location in the cache 16 or NVS 18 to which source datais written or the location in the sequence buffer 20 to which data readfrom cache 16 is transferred or the location in the cache 16 from whichread data is transferred before being returned to the host 2; the bytecount 58 indicates the number of bytes to be transferred. The source 54and destination address 56 may indicate a page and offset into the pagewhere the data to transfer begins. A conversion operation 60 fieldindicates a conversion operation to perform on data subject to the DMAtransfer operation, such as adding metadata or removing metadata fromthe data at the source address 52 before writing the data to thedestination address 56.

FIG. 4 illustrates an embodiment of operations performed by the adaptorcontroller 2 and DMA engine 24 to write a logical track received fromthe host 2 to memory. Upon receiving (at block 100) at the adaptor 8 aplurality of blocks of data in a logical track to write to the storagesystem 4, the adaptor controller 22 determines (at block 102) pages(i.e., page IDs of physical pages) in a first memory device, e.g., cache16. In one embodiment, the pages may be determined by sending (at block102) a request to the processor 12 for the pages and receiving (at block104) from the processor 12 pages in the cache 16 to store the logicalblocks, wherein the pages may be discontiguous. In one embodiment, theprocessor 12 may automatically return enough pages to store all thelogical blocks in a logical track for a track write operation. Thus, ifa logical track to write has 128 blocks, each logical block plusmetadata is 524 bytes, and each page is 4 KB, then the processor 12returns seventeen free pages for the adaptor controller 22 to use. Theadaptor controller 22 then adds (at block 106) the blocks of data to thebuffer 20. Thus, the host 2 may be held off from sending the data to theadaptor buffer 20 until indication of pages to use are received by theadaptor 8.

The adaptor controller 22 indicates (at block 108) in a data structure,e.g., page mapping 26, in the adaptor 8 a mapping of the blocks in thelogical track to write to the physical pages in the first memory device.Consecutive blocks in the logical track may map to discontiguousphysical pages in the memory device 16. The adaptor controller 22 usesthe page mapping 26 to generate (at block 110) DMA I/O requests to writethe blocks in the buffer 20 to the determined pages in the first memorydevice, e.g., the cache 16. Two I/O requests are generated to write theblock split between two pages in the memory device 16. The generated I/Orequests are then executed (at block 112) in the adaptor 8 to write theblocks in the buffer (including appended metadata) to the determinedpages in the first memory device, such as the cache 16. In oneembodiment, the DMA engine 24 executes the I/O requests to write theblocks directly to the cache 16.

The adaptor controller 22 may further perform operations to write theupdated blocks to a second memory device, such as the NVS 18 bydetermining (at block 114) pages in a second memory device, e.g., NVS18. As with the cache 16, the adaptor controller 22 may determine thepages to write the data by requesting pages in the NVS 18 from theprocessor 12. The adaptor controller 22 generates (at block 116) I/Orequests to write the blocks in the buffer to the determined pages inthe second memory device (NVS 18), wherein two I/O requests aregenerated to write the block split between two pages in the secondmemory device (NVS 18). The DMA engine 24 in the adaptor 8 executes (atblock 118) the generated I/O requests to write the blocks in the buffer20 to the determined pages in the second memory device, e.g., NVS 18. Inthis way, the host adaptor 8 generates I/O requests to write an updatedlogical track to both cache 16 and NVS 18.

In one embodiment, the adaptor controller 22 may return (at block 120)to the processor 12 indication of at least one identifier of at leastone page to which blocks were not written. In response to thisindication, the processor 12 may free the pages identified in thereturned indication because these pages were not written to by theadaptor. For instance, the processor may provide the controller 22 afixed number of pages capable of including all blocks in a logicaltrack, such as all 128 blocks. If the host 2 did not request to write toall blocks in a logical track, then those pages not used for the writemay be freed. The indication of the pages to free may comprise a bitmapindicating those tracks not written to and those tracks written to. Theprocessor 12 may then determine the pages to which blocks were notwritten by mapping the blocks written to as indicated in the bitmap tothe pages the processor 12 provide to the controller 22 to use, andthose provided pages to which written blocks did not map may be freed.

FIG. 5 illustrates one embodiment of how the adaptor controller 22generates the I/O requests to write the blocks to pages in the cache 16and append metadata to the blocks as they are being written into thecache 16 and/or NVS 18. The operations of FIG. 5 may be performed atblocks 110 and 116 in FIG. 5. Upon initiating the operation to generatethe I/O requests (at block 150), the adaptor controller 22 processes (atblock 152) the blocks for a logical track sequentially, as indicated inthe page mapping 26 and performs the operations at blocks 154-160. Theadaptor controller 22 generates (at block 154) one I/O request forconsecutive (non-split) blocks in the buffer 20 that map to one page asindicated in the mapping 26, where the I/O request specifies to addmetadata to the blocks while they are being written to the determinedpages. In one embodiment, the I/O request may comprise a DMA request 50,where the conversion operation 60 field indicates to add metadata to theblock being written. One I/O request is then generated (at block 156) towrite a split block (if there is one) following the just writtennon-split consecutive blocks to a split buffer 21 in the adaptor 8 andadd metadata as part of the write. After the metadata is added, one I/Orequest is generated (at block 158) to write a first portion of thesplit block in the split buffer 21 to the page to which the firstportion maps and one I/O request is generated (at block 160) to write asecond portion of the split block in the split buffer 21 to a next pageto which the second portion maps. If (at block 162) there are stillfurther logical blocks indicated in the page mapping 26 to write tofurther pages, then control returns to block 154 to generate one or moreI/O requests to write the remainder of the logical blocks to one or morepages. Otherwise, if I/O requests, e.g., DMA write requests, have beengenerated for all logical blocks indicated in the page mapping 26, thenthe process of generating I/O requests ends.

FIG. 6 illustrates an embodiment of operations to process a read requestfrom a host 2. Upon receiving (at block 200) a read request from a host2 for a plurality of blocks of data, which may span one logical track,the adaptor controller 22 determines (at block 202) pages in a memorydevice, e.g., cache 16, including the requested data. In one embodiment,the pages may be determined by the adaptor controller 22 by sending (atblock 202) a request to the processor 12 for pages including therequested blocks. The controller 22 receives (at block 204) from theprocessor 12 indication of at least one page including the requestedblocks. The controller 22 generates I/O requests to read the blocks fromthe determined pages in the memory device, e.g., cache 16, into abuffer, e.g., the sequence buffer 20, in the adaptor 8. At least one ofthe blocks is split between two pages in the cache 16. The I/O requestsmay comprise DMA requests for the DMA engine 24. Blocks 206-218 provideone embodiment to generate the I/O requests.

At block 206, a page is set to the first page of the received pages. Theadaptor controller 22 generates (at block 208) one I/O request to readto the buffer 20 all consecutive (non-split) requested blocks in thepage, where the I/O requests specify to remove metadata from the blockswhile they are being written to the buffer. The operation to removemetadata from the blocks as they are written may be indicated in theconversion operation field 60. One I/O request is generated (at block210) for the requested split block in the page to read a first portionof the split block in the page to a split buffer 21 in the adaptor 8 andgenerates (at block 212) one I/O request for the split block to read asecond portion of the block to the next page of the split buffer 2 1.The adaptor controller 22 then generates (at block 214) one I/O requestfor the split block reassembled in the split buffer 21 to remove themetadata from the split block and write to the buffer 20 following thenon-split blocks written to the buffer 20. Thus, the 524 byte blocksread into the split buffer 21 having the metadata may be reduced to 512byte blocks stripped of their metadata to write to the buffer 20 andreturn to the host 2. If (at block 216) there is a next page of thedetermined pages to process, then the page is set (at block 218) to thenext page of the determined pages. In generating the I/O requests, thecontroller 22 may construct a page mapping 26 of blocks to the pagesreturned by the processor. If the first requested block to read is at anoffset within the first returned page, i.e., not the first block of thelogical track included in the first page, then the controller 22includes in the first I/O request the offset in the page where the firstrequested block is located.

If there are no further pages to read from, then the adaptor controller22 executes (at block 220) the generated I/O requests to read the blocksfrom the determined pages in the memory device, e.g., cache 16, into thebuffer 20, the adaptor 8, such as the DMA engine 24, executes (at block222) the generated I/O requests to read the blocks from the determinedpages in the memory device, e.g., cache 16, into the buffer 20. The dataread in response to executing one I/O request is appended to the datafrom the read request previously read into the sequence buffer 20. Theblocks in the buffer 20 are transmitted (at block 212) to a host 2requesting the blocks over a network in response to removing themetadata from the blocks. In this embodiment, the operations to add andremove metadata are performed in the adaptor 8.

With the described embodiments, the host adaptor 8 handles the mappingof logical blocks to physical pages in the memory device(s) to which theI/O request is directed. The adaptor then transfers the data directly tothe memory to bypass the processor 12. In the described embodiments, thehost adaptor 8 queries the processor 12 to determine physical pages inthe memory device to use for the I/O request. Further, in oneembodiment, the generated I/O requests may retrieve or write to blocksthat span multiple pages in separate I/O requests.

Additional Embodiment Details

The described embodiments may be implemented as a method, apparatus orarticle of manufacture using standard programming and/or engineeringtechniques to produce software, firmware, hardware, or any combinationthereof. The term “article of manufacture” as used herein refers to codeor logic implemented in hardware logic (e.g., an integrated circuitchip, Programmable Gate Array (PGA), Application Specific IntegratedCircuit (ASIC), etc.) or a computer readable medium, such as magneticstorage medium (e.g., hard disk drives, floppy disks,, tape, etc.),optical storage (CD-ROMs, optical disks, etc.), volatile andnon-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs,SRAMs, firmware, programmable logic, etc.). Code in the computerreadable medium is accessed and executed by a processor. The code inwhich preferred embodiments are implemented may further be accessiblethrough a transmission media or from a file server over a network. Insuch cases, the article of manufacture in which the code is implementedmay comprise a transmission media, such as a network transmission line,wireless transmission media, signals propagating through space, radiowaves, infrared signals, etc. Thus, the “article of manufacture” maycomprise the medium in which the code is embodied. Additionally, the“article of manufacture” may comprise a combination of hardware andsoftware components in which the code is embodied, processed, andexecuted. Of course, those skilled in the art will recognize that manymodifications may be made to this configuration without departing fromthe scope of the present invention, and that the article of manufacturemay comprise any information bearing medium known in the art.

FIGS. 2 and 3 show certain information included in a page mapping andDMA request. In alternative embodiments, this information may be storedin different data structures having different formats and informationthan shown.

Certain embodiments may be directed to a method for deploying computinginstructions by a person or automated processing integratingcomputer-readable code into a computing system, wherein the code incombination with the computing system is enabled to perform theoperations of the described embodiments.

The illustrated operations of FIGS. 4, 5, and 6 show certain eventsoccurring in a certain order. In alternative embodiments, certainoperations may be performed in a different order, modified or removed.Moreover, steps may be added to the above described logic and stillconform to the described embodiments. Further, operations describedherein may occur sequentially or certain operations may be processed inparallel. Yet further, operations may be performed by a singleprocessing unit or by distributed processing units.

The foregoing description of various embodiments of the invention hasbeen presented for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseform disclosed. Many modifications and variations are possible in lightof the above teaching. It is intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto. The above specification, examples and data provide acomplete description of the manufacture and use of the composition ofthe invention. Since many embodiments of the invention can be madewithout departing from the spirit and scope of the invention, theinvention resides in the claims hereinafter appended.

1. A method, comprising: receiving at an adaptor a plurality of blocksof data to write to storage; adding the blocks of data to a buffer inthe adaptor; determining pages in a memory device; generating I/Orequests to write the blocks in the buffer to the determined pages,wherein two I/O requests are generated to write to one block splitbetween two pages in the memory device; and executing in the adaptor thegenerated I/O requests to write the blocks in the buffer to thedetermined pages in the memory device.
 2. Then method of claim 1,wherein the received blocks comprise blocks within a logical track, andwherein the determined pages comprise identifiers of physical pages inthe memory device, further comprising: indicating in a data structure inthe adaptor a mapping of the blocks in the logical track to the physicalpages, wherein consecutive blocks in the logical track may be mapped todiscontiguous physical pages in the memory device, and wherein the datastructure is used to generate the I/O requests.
 3. The method of claim1, wherein determining the pages comprises: sending a request to aprocessor for pages to write the blocks; and receiving from theprocessor identifiers of pages to store the blocks, wherein the pagesmay be discontiguous.
 4. The method of claim 3, wherein the identifiedpages may comprise a fixed number of pages capable of including allblocks in a logical track, and further comprising: returning to theprocessor indication of at least one identifier of at least one page towhich blocks were not written, wherein the processor frees the pagesidentified in the returned indication.
 5. The method of claim 1, furthercomprising: appending metadata to the blocks written to the pages in thememory device.
 6. The method of claim 1, wherein generating the I/Orequests comprises: generating an I/O request to write a set of theblocks in the buffer to one determined page in the memory device;generating an I/O request to write a first portion of a split block inthe buffer following the set of the blocks to the determined page in thememory device; generating an I/O request to write a second portion ofthe split block in the buffer to a next determined page in the memorydevice, wherein the second portion does not fit into the determinedpage; repeating the operations of generating the I/O request to writeblocks starting from the next determined page until I/O requests aregenerated to consecutively write all the blocks in the buffer to thedetermined pages.
 7. The method of claim 6, wherein the I/O requestwriting the set of blocks to one page appends metadata to the blockswhile writing the blocks to the page.
 8. The method of claim 7, whereinappending the metadata to the split blocks comprises: generating an I/Orequest to write the split block in the buffer to a split buffer withinthe buffer; appending the metadata to the split block in the splitbuffer, wherein the I/O requests to write the first and second portionsof the split block write the first and second portions and the metadatafrom the split buffer.
 9. The method of claim 1, wherein the memorydevice comprises a first memory device, further comprising: determiningpages in a second memory device; generating I/O requests to write theblocks in the buffer to the determined pages in the second memorydevice, wherein at least one block is split between two pages in thesecond memory device; executing in the adaptor the generated I/Orequests to write the blocks in the buffer to the determined pages inthe second memory device.
 10. The method of claim 1, wherein the I/Orequests comprise Direct Memory Access (DMA) requests executed by a DMAengine in the adaptor.
 11. A method, comprising: receiving a readrequest for plurality of blocks of data; determining pages in a memorydevice including the requested blocks; generating I/O requests to readthe blocks from the determined pages in the memory device into a bufferin the adaptor, wherein at least one of the blocks is split between twopages in the memory device; and executing in the adaptor the generatedI/O requests to read the blocks from the determined pages in the memorydevice into the buffer.
 12. The method of claim 11, wherein determiningthe pages in the memory comprises: sending a request to a processor forpages including the requested blocks; and receiving from the processorindication of at least one page including the requested blocks, whereinthe determined pages comprise the received indicated pages.
 13. Themethod of claim 11, wherein the blocks in the pages include metadata,further comprising: removing the metadata from blocks in the pages readinto the buffer.
 14. The method of claim 11, wherein generating the I/Orequests further comprises: generating an I/O request to read to thebuffer requested blocks in one determined page; generating an I/Orequest to read to a split buffer in the buffer a first portion of asplit block in the determined page; generating an I/O request to read tothe split buffer a second portion of the split block in a nextdetermined page in the memory device, wherein the second portion doesnot fit into the determined page; generating an I/O request to read thesplit block in the split buffer into the buffer; and repeating theoperations of generating the I/O requests to read the requested blocksfrom the determined pages consecutively into the buffer.
 15. The methodof claim 14, wherein the I/O request reading the split block from thesplit buffer removes the metadata from the split block before the blockis read into the buffer.
 16. The method of claim 11, further comprising:transmitting the blocks in the buffer to a host system requesting theblocks over a network in response to removing the metadata from theblocks.
 17. A system in communication with storage, comprising: a memorydevice; a processor in communication with the memory device; an adaptorin communication with the memory device and the processor and having abuffer adaptor, wherein the adaptor is capable of causing operations,the operations comprising: (a) receiving a plurality of blocks of datato write to the storage; (b) adding the blocks of data to the adaptorbuffer; (c) determining, from the processor, pages in the memory device;(d) generating I/O requests to write the blocks in the adaptor buffer tothe determined pages, wherein two I/O requests are generated to write toone block split between two pages in the memory device; and (e)executing in the adaptor the generated I/O requests to write the blocksin the buffer to the determined pages in the memory device.
 18. Thensystem of claim 17, wherein the received blocks comprise blocks within alogical track, and wherein the determined pages comprise identifiers ofphysical pages in the memory device, wherein the adaptor is furthercapable of causing operations comprising: indicating in a data structurea mapping of the blocks in the logical track to the physical pages,wherein consecutive blocks in the logical track may be mapped todiscontiguous physical pages in the memory device, and wherein the datastructure is used to generate the I/O requests.
 19. The system of claim17, wherein determining the pages comprises: sending a request to aprocessor for pages to write the blocks; and receiving from theprocessor identifiers of pages to store the blocks, wherein the pagesmay be discontiguous.
 20. The system of claim 19, wherein the identifiedpages may comprise a fixed number of pages capable of including allblocks in a logical track, and wherein the adaptor is further capable ofcausing operations comprising: returning to the processor indication ofat least one identifier of at least one page to which blocks were notwritten, wherein the processor frees the pages identified in thereturned indication.
 21. The system of claim 17, wherein the adaptor isfurther capable of causing operations comprising: appending metadata tothe blocks written to the pages in the memory device.
 22. The system ofclaim 17, wherein generating the I/O requests comprises: generating anI/O request to write a set of the blocks in the buffer to one determinedpage in the memory device; generating an I/O request to write a firstportion of a split block in the buffer following the set of the blocksto the determined page in the memory device; generating an I/O requestto write a second portion of the split block in the buffer to a nextdetermined page in the memory device, wherein the second portion doesnot fit into the determined page; repeating the operations of generatingthe I/O request to write blocks starting from the next determined pageuntil I/O requests are generated to consecutively write all the blocksin the buffer to the determined pages.
 23. A system, comprising: amemory device; a processor in communication with the memory device; andan adaptor in communication with the memory device and the processor andhaving a buffer adaptor, wherein the adaptor is capable of causingoperations, the operations comprising: (a) receiving a read request forplurality of blocks of data; (b) determining pages in a memory deviceincluding the requested blocks; (c) generating I/O requests to read theblocks from the determined pages in the memory device into a buffer inthe adaptor, wherein at least one of the blocks is split between twopages in the memory device; and (d) executing the generated I/O requeststo read the blocks from the determined pages in the memory device intothe buffer.
 24. The system of claim 23, wherein determining the pages inthe memory comprises: sending a request to a processor for pagesincluding the requested blocks; and receiving from the processorindication of at least one page including the requested blocks, whereinthe determined pages comprise the received indicated pages.
 25. Thesystem of claim 23, wherein the blocks in the pages include metadata,and wherein the adaptor is further capable of causing operationscomprising: removing the metadata from blocks in the pages read into thebuffer.
 26. The system of claim 23, wherein generating the I/O requestsfurther comprises: generating an I/O request to read to the bufferrequested blocks in one determined page; generating an I/O request toread to a split buffer in the buffer a first portion of a split block inthe determined page; generating an I/O request to read to the splitbuffer a second portion of the split block in a next determined page inthe memory device, wherein the second portion does not fit into thedetermined page; generating an I/O request to read the split block inthe split buffer into the buffer; and repeating the operations ofgenerating the I/O requests to read the requested blocks from thedetermined pages consecutively into the buffer.
 27. The system of claim26, wherein the I/O request reading the split block from the splitbuffer removes the metadata from the split block before the block isread into the buffer.
 28. An article of manufacture capable of causingoperations to be performed in an adaptor, wherein the operations are incommunication with a buffer in the adaptor and a memory device cachingdata for a storage, wherein the operations comprise: receiving aplurality of blocks of data to write to the storage; adding the blocksof data to the buffer; determining pages in the memory device;generating I/O requests to write the blocks in the buffer to thedetermined pages, wherein two I/O requests are generated to write to oneblock split between two pages in the memory device; and executing thegenerated I/O requests to write the blocks in the buffer to thedetermined pages in the memory device.
 29. Then article of manufactureof claim 28, wherein the received blocks comprise blocks within alogical track, and wherein the determined pages comprise identifiers ofphysical pages in the memory device, wherein the operations furthercomprise: indicating in a data structure in the adaptor a mapping of theblocks in the logical track to the physical pages, wherein consecutiveblocks in the logical track may be mapped to discontiguous physicalpages in the memory device, and wherein the data structure is used togenerate the I/O requests.
 30. Then article of manufacture of claim 28,wherein the operations are further in communication with a processor,wherein determining the pages comprises: sending a request to theprocessor for pages to write the blocks; and receiving from theprocessor identifiers of pages to store the blocks, wherein the pagesmay be discontiguous.
 31. Then article of manufacture of claim 30,wherein the identified pages may comprise a fixed number of pagescapable of including all blocks in a logical track, and wherein theoperations further comprise: returning to the processor indication of atleast one identifier of at least one page to which blocks were notwritten, wherein the processor frees the pages identified in thereturned indication.
 32. Then article of manufacture of claim 28,wherein the operations further comprise: appending metadata to theblocks written to the pages in the memory device.
 33. Then article ofmanufacture of claim 28, wherein generating the I/O requests comprises:generating an I/O request to write a set of the blocks in the buffer toone determined page in the memory device; generating an I/O request towrite a first portion of a split block in the buffer following the setof the blocks to the determined page in the memory device; generating anI/O request to write a second portion of the split block in the bufferto a next determined page in the memory device, wherein the secondportion does not fit into the determined page; repeating the operationsof generating the I/O request to write blocks starting from the nextdetermined page until I/O requests are generated to consecutively writeall the blocks in the buffer to the determined pages.
 34. Then articleof manufacture of claim 33, wherein the I/O request writing the set ofblocks to one page appends metadata to the blocks while writing theblocks to the page.
 35. Then article of manufacture of claim 34, whereinthe operations are further in communication with a split buffer withinthe buffer, wherein appending the metadata to the split blockscomprises: generating an I/O request to write the split block in thebuffer to the split buffer; and appending the metadata to the splitblock in the split buffer, wherein the I/O requests to write the firstand second portions of the split block write the first and secondportions and the metadata from the split buffer.
 36. Then article ofmanufacture of claim 28, wherein the memory device comprises a firstmemory device, wherein the operations are further in communication witha second memory device, and wherein the operations further comprise:determining pages in the second memory device; generating I/O requeststo write the blocks in the buffer to the determined pages in the secondmemory device, wherein at least one block is split between two pages inthe second memory device; executing in the adaptor the generated I/Orequests to write the blocks in the buffer to the determined pages inthe second memory device.
 37. Then article of manufacture of claim 28,wherein the I/O requests comprise Direct Memory Access (DMA) requestsexecuted by a DMA engine in the adaptor.
 38. An article of manufacturecapable of causing operations to be performed in an adaptor, wherein theoperations are in communication with a buffer in the adaptor and amemory device caching data for a storage, wherein the operationscomprise: receiving a read request for plurality of blocks of data;determining pages in the memory device including the requested blocks;generating I/O requests to read the blocks from the determined pages inthe memory device into the buffer, wherein at least one of the blocks issplit between two pages in the memory device; and executing in theadaptor the generated I/O requests to read the blocks from thedetermined pages in the memory device into the buffer.
 39. The articleof manufacture of claim 38, wherein determining the pages in the memorycomprises: sending a request to a processor for pages including therequested blocks; and receiving from the processor indication of atleast one page including the requested blocks, wherein the determinedpages comprise the received indicated pages.
 40. The article ofmanufacture of claim 38, wherein the blocks in the pages includemetadata, wherein the operations further comprise: removing the metadatafrom blocks in the pages read into the buffer.
 41. The article ofmanufacture of claim 38, wherein the operations are further incommunication with a split buffer in the buffer, and wherein generatingthe I/O requests further comprises: generating an I/O request to read tothe buffer requested blocks in one determined page; generating an I/Orequest to read to the split buffer a first portion of a split block inthe determined page; generating an I/O request to read to the splitbuffer a second portion of the split block in a next determined page inthe memory device, wherein the second portion does not fit into thedetermined page; generating an I/O request to read the split block inthe split buffer into the buffer; and repeating the operations ofgenerating the I/O requests to read the requested blocks from thedetermined pages consecutively into the buffer.
 42. The article ofmanufacture of claim 41, wherein the I/O request reading the split blockfrom the split buffer removes the metadata from the split block beforethe block is read into the buffer.
 43. The article of manufacture ofclaim 38, further comprising: transmitting the blocks in the buffer to ahost system requesting the blocks over a network in response to removingthe metadata from the blocks.
 44. A method for deploying computinginstructions, comprising integrating computer-readable code into a firstand second processing complexes, wherein the code in combination withthe first and second processing complexes is enabled to cause the firstand second processing complexes to perform: receiving at an adaptor aplurality of blocks of data to write to storage; adding the blocks ofdata to a buffer in the adaptor; determining pages in a memory device;generating I/O requests to write the blocks in the buffer to thedetermined pages, wherein two I/O requests are generated to write to oneblock split between two pages in the memory device; and executing in theadaptor the generated I/O requests to write the blocks in the buffer tothe determined pages in the memory device.
 45. The method of claim 44,further comprising: appending metadata to the blocks written to thepages in the memory device.
 46. The method of claim 44, whereingenerating the I/O requests comprises: generating an I/O request towrite a set of the blocks in the buffer to one determined page in thememory device; generating an I/O request to write a first portion of asplit block in the buffer following the set of the blocks to thedetermined page in the memory device; generating an I/O request to writea second portion of the split block in the buffer to a next determinedpage in the memory device, wherein the second portion does not fit intothe determined page; repeating the operations of generating the I/Orequest to write blocks starting from the next determined page until I/Orequests are generated to consecutively write all the blocks in thebuffer to the determined pages.